The present invention is directed to electronic circuitry and, more particularly, to voltage level shifters.
A semiconductor device, such as an integrated circuit (IC) or the like, may operate using multiple voltage levels. For example, an IC may have multiple internal modules having different functions and that require different operating voltages. A voltage level shifter is a circuit that is used to convert signal levels to higher or lower voltages.
Conventional level shifters include a latch connected to a supply voltage and having two branches, each including a p-type metal-oxide-semiconductor (MOS) or “PMOS” transistor. Each branch is connected to its own output node, and the gate of each PMOS transistor is coupled to the output node of the opposite branch. An n-type MOS or “NMOS” transistor is connected in series between the respective channel and a second voltage, such as ground. During operation, one output node is connected to the supply voltage via the corresponding PMOS transistor while the other output node is pulled to ground via the respective NMOS transistor.
However, complications arise during switching operations. The activation and deactivation of the transistors, particularly of the PMOS transistors, is not instantaneous. Thus, during switching, an output may be charged through the corresponding PMOS transistor while simultaneously being discharged through the respective NMOS transistor. This results in a delay in discharging the output node, and higher power consumption. In addition, the direct path created between the supply voltage and ground through the activated PMOS and NMOS transistors creates a phenomenon of “cross-bar current,” which further degrades the circuit performance.
It is therefore desirable to provide a level shifter with improved switching speed, reduces cross-bar current, and consumes less power.